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| Plerow APL2030 PLL Module Features * +4 dBm Output Level at 2030 MHz * Channel Step Size : 200 kHz *2 nd Description The plerow PLL synthesizer module was designed for use in wireless and wireline systems in a wide range of frequency from 50 MHz to 6 GHz. ASB's PLL provides exceptionally low spurious and phase noise performance with fast locking time and low current consumption. All products are available in a surface-mount type package. TM Harmonic : < -20 dBc < 10 ms * Spurious Level : < -70 dBc * Lock Time : * 20 mA Current Consumption Specifications Parameter Frequency Range Output Power Supply Voltage Current Consumption Channel Step Size 2nd Harmonics Spurious Level Lock Time Reference Frequency Reference Input Level Phase Noise (C / N) @ 10 kHz @ 100 kHz Output Impedance Operating Temp. Range Package Type & Size dBc/Hz dBc/Hz C mm -40 -108 -123 -105 -120 50 25 SMT, 19.0Wx19.0Lx5.8H 85 -102 -117 Unit MHz dBm V mA kHz dBc dBc ms MHz dBm -5 10 Min. 2020 2 4.7 Typical 2030 3 5.0 20 100 -25 -78 3 10 0 5 Max. 2040 4 5.3 30 1000 -20 -70 10 More Information Website: www.asb.co.kr E-mail: sales@asb.co.kr Tel: (82) 42-528-7220 Fax: (82) 42-528-7222 ASB, Inc., 4th Fl. Venture Town Bldg, KT HRDC, 367-17 Goijeong-Dong, Seo-Gu, Daejeon, 302-716, Korea 1) Measurement conditions are as follows: T = 25C, VCC = 5 V, Freq. = 2030 MHz, 50 ohm system. Outline Drawing Top View Bottom View Pin Configuration Dimension (mm) A 19.0 B 19.0 C 5.8 D 1.5 E 0.5 F 1.75 G 1.35 H 15.0 I 0.9 Tolerance: 0.2 D A E F I C B Side View 1/1 www.asb.co.kr H G 1 2 3 4 9 13 15 16 Others CLOCK DATA ENABLE OSC IN VCC (VCO) RF OUT VCP (PLL) LOCK DETECT Ground March 2004 |
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